The subject matter of the present application relates to semiconductor devices of integrated circuits and their fabrication, particularly field effect transistors.
One of the ways proposed to improve performance in complementary metal oxide semiconductor (“CMOS”) technology integrated circuits is to provide a high dielectric constant, i.e., “high-k” gate dielectric layer, for n-type and p-type field effect transistors (“NFET” and “PFET” devices), and to form metal gates of the NFET and PFET devices.
However, differences in the workfunctions of NFET and PFET devices typically require different metal layers to be provided in the gates of respective N- or P-type transistors. In addition, making the same type of FET (meaning both N or both P) having different threshold voltages is desirable. Heretofore, methods for forming the gates of N- and P-type transistors have been cumbersome. Further improvements in the fabrication of N- and P-type transistors having metal gates are needed as well as further improvements in the fabrication of multi-threshold transistors having metal gates.